![]() ![]() (And yes, the GaN SOI parts should use a different symbol to reflect this - I believe the manufacturer's recommended symbol is the traditional one, omitting the arrow and substrate connection since they are indeed physically absent. The similar behavior arises from Vgs(off) being fixed, since sufficient reverse bias simply turns it on in inverted mode, as any regular FET ought to (but usually doesn't because body diode Vf << Vgs(th)). Even the GaN SOI (semi-on-insulator) parts, that well and truly do not have a channel-substrate junction - for familiarity's sake, they are still rated as if they have them. RF transistors are rarely rated in usual terms, anyway. Possibly RF parts, but that might be as much because, if you inject charge carriers into the slow-ass substrate junction, it freezes up like a PIN diode. I haven't seen a single power FET that isn't rated for full forward current in the body diode. It's also common to see a MOSFET symbol with an antiparallel diode, but this is also almost always erroneous there is no additional diode in the device, and the body diode action is already spelled out in the traditional insulated-gate-over-three-line-segments-with-arrow shape (which, apparently, all are quick to forget that it's actually telling you about that very diode to begin with). They also typically leave off the bounding circle, which I have always interpreted as the boundary of the chip so that in an IC, everything should be drawn within some other bounding shape (usually a rectangle), but in a discrete design, all individual devices should be encircled. There's also little to no distinction between kinds of MOSFETs, as they will most likely all be identical process (N/P and size (width/length) being the only variables). Of particular note, the substrate connection is almost always strapped to VSS/VDD, so it can be omitted. The transistor size is one finger of 10u * 120n.Note that IC schematics traditionally use the shorthand of a simplified symbol (the insulated-gate-over-a-channel above, or an erroneous BJT-with-square-arrows one), because they use a metric shitload (that's a technical term) of them. My simulation differs from the OP's by using a swing of 1 V, rather than 3 V, to meet the requirements of my VLSI process. The following ADEXL + Spectre-MMSIM simulation confirms this behavior: As long as VGATE is greater than the lower of VIN and VOUT, the channel can form an inversion layer and current can flow. Note that while the transistor is drawn as shown with the source on the left, the transistor is really a symmetric device with a channel and a gate. When VGATE is low, the transistor does not conduct and the output voltage is held at the same level (until it decays by leakage). When VGATE is high, the transistor conducts and CLOAD tracks the input voltage. Simulate this circuit – Schematic created using CircuitLabĬLOAD can either be an explicit capacitor that you place intentionally, or simply be the parasitic capacitances of M1's channel and/or input capacitance of the following stage's input transistor (if this were cascaded in a signal chain). You've likely created a sample-and-hold circuit, presumably because the load of your switch has some capacitance but does not draw current: ![]()
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